|
ASIC
Application Specific Integrated Circuit. A custom chip that uses
fixed logic.
Cores
In the semiconductor design industry, refers to predefined
functions such as processors or bus interfaces that are typically
licensed from the software developer. Cores can be implemented
directly in silicon, either in fixed logic or programmable logic
devices, and saves chip designers time during product development.
Synonymous with Intellectual Property.
CPLD
A Complex Programmable Logic Device. Logic densities usually less
than 10,000 gates.
DSP
Digital Signal Processing. Can take place in dedicated DSP
processors, fixed logic ASICs, or programmable logic devices. Some
of the highest performing DSP systems are implemented in FPGAs
because processing can be done on the chips in a parallel
fashion.
Design
Entry
The methodology designers use to create a chip, for example,
schematic or hardware definition language.
EDA
Electronic Design Automation. Refers to a broad array of front-end
(design entry) and backend (implementation) software tools used to
create, simulate, verify and test the circuitry in chips.
Fabless
A semiconductor company that does not own or operate its own
silicon wafer fabrication foundries but instead outsources
manufacturing.
Fibre
Channel
A high-bandwidth serial standard offering 1.06 Gbit/second
transfer rates scalable to 2.12 or 4.24 Gbit/second. Capable of
carrying multiple existing interface command sets, including
Internet Protocol (IP), SCSI, IPI, HIPPI-FP, and audio/video.
FPGA
Field Programmable Gate Array. Invented by Xilinx in 1984. Gate
counts now in the millions, with high level of system functions -
processors, delay lock loops, clock managers, memory, serial
transceivers -- integrated on a single FPGA chip.
InfiniBand
A new industry I/O specification using a 2.5 Gbit/seceond wire
speed connection with one, four or twelve wire link widths.
Applications include remote storage devices and servers.
Interconnect
In programmable logic, silicon devoted to connecting memory
elements on the chip to create a logic circuit.
I/O
Input/output. The physical connections, and the various electrical
standards, for getting signals on and off a chip.
IP
Intellectual property. In the semiconductor design industry,
refers to predefined functions such as processors or bus interfaces
that are typically licensed from the software developer. IP can be
implemented directly in silicon, either in fixed logic or
programmable logic devices, and saves chip designers time during
product development. Synonymous with Cores.
LDT
Lightning Data Transport, a chip-to-chip interconnect that
provides a bandwidth from 6.4 Gb/sec per eight wire link width, and
can support up to 32 links.
LUT
Look up table. When combined with one or more flip flops,
constitutes the basic memory-based programmable logic element in
FPGAs.
MAC
Multiply and accumulate. A measure of arithmetical performance in
digital signal processing systems. FPGAs can achieve some of the
highest DSP performance, calculating a half trillion MACs per
second.
NRE
Non-recurring Engineering. In the world of fixed logic chip
design, refers to the one-time, up front costs customers incur in
designing a chip. Includes software tools, engineering time, design
verification, mask sets and prototypes. In the programmable logic
world, usually refers to the expenses associated with converting a
PLD design to a fixed logic design to gain a cost reduction.
PAL
Programmable Array Logic. The earliest and, in terms of logic
density, the simplest form of a programmable logic device.
Place and
Route
Using backend implementation software tools, the process of
connecting various memory elements in an FPGA to create a custom
logic circuit.
Platform
FPGA
Standard FPGAs that are targeted at multiple applications such as
embedded processing, digital signal processing. Xilinx Virtex-II
family was the first embodiment of Platform FPGAs.
PLD
Any programmable logic device. Encompasses PALs, SPLDs, CPLDs and
FPGAs.
POS-PHY4
Also, PL4. A 13.3 Gbit/second parallel link layer to physical
layer interface for packet and cell transfer over SONET for OC-192c
and 10 G bit/second Ethernet applications. POS-PHY4 is a 16-bit
point-to-point interconnect with 832 Mb/sec per bit signaling
utilizing double data rate clocking.
Product
Term
The basic memory-based programmable logic element in CPLDs.
Reconfigurable
Computing
A methodology of using programmable logic devices in a system
design such that the hardware-based logic can be changed to perform
various tasks. Benefits includes the use of fewer components, less
power, and the flexibility that bring about. Also allows networked
equipment in the field to be upgraded or repaired remotely.
RapidIO
A next-generation switched-fabric interconnect architecture for
embedded systems that is optimized for both high bandwidth and low
latency. Initial implementations are expected to exceed 1.0
Gbit/second throughput based on clock rates from 250 MHz and
higher. Applications will include embedded systems in the
networking, multimedia, storage and signal-processing sectors.
XAUI
A quad transceiver utilizing 3.125 Gbit/second serial links to
create a 10 gigabit attachment unit interface (XAUI). Multiple XAUI
interfaces can be implemented to allow a single chip to interface
to both 10 Gigabit Ethernet and OC-192c.
|
