FOR IMMEDIATE RELEASE

XILINX ENABLES NEXT GENERATION METRO AREA NETWORKS BY DELIVERING ETHERNET OVER SONET/SDH SOLUTIONS
XILINX and AMIRIX deliver reference design to aggregate multiple Gigabit Ethernet ports to single SPI-4.2 interface with optional GFP-F

SAN JOSE, Calif., December 17, 2003 - Xilinx, Inc., (NASDAQ:XLNX), the world leader in programmable logic solutions and AMIRIX Systems, a leading provider of embedded systems design services, today announced the immediate availability of a free, fully functional reference design targeted for the metro and edge equipment markets. The Ethernet Aggregation Reference Design provides SONET/SDH equipment designers with integrated solutions, with flexible GFP processing functions as well as support for different Gigabit Ethernet to SONET port configuration. The reference design integrates all necessary functions for the application, such as the Gigabit Ethernet MACs, SPI-4.2 interface, optional Frame Mapped GFP adaptation, traffic management, and control plane functions.

"The Virtex-II Pro and Xilinx IP cores, along with our extensive experience, allowed us to develop this complex system and test it in hardware quickly and effectively," said Bruce Oakley, Director of Embedded Systems Design at AMIRIX Systems. "The reference design forms an excellent platform which can be customized quickly to suit the needs of real world applications."

The design utilizes Virtex-II Pro embedded RocketIO serial transceivers to implement standard PHY modules for Gigabit Ethernet. The embedded PowerPC 405 microprocessor provides control plane management functions, including Ethernet port statistics-gathering, and data plane status and control, with no external memory. In addition, the design takes advantage of the Virtex-II Pro high density and high performance FPGA fabric, embedded memory and SelectIO™ parallel I/O technology to deliver a flexible solution. Utilizing the Xilinx Virtex-II Pro Platform FPGA, this reference design provides metro and edge equipment system designers with high performance integration using RocketIO Transceivers, logic, PowerPC, BlockRAM and LVDS I/Os. The design also uses proven robust SPI-4.2 and Gigabit Ethernet LogiCore™ IP blocks.

"The RocketIO and PowerPC features in the Virtex-II Pro enable Xilinx to target markets such as metro and edge access with performance programmable solutions," said Robert Bielby, senior director of Strategic Marketing Solutions at Xilinx. "The AMIRIX and Xilinx teams partnered together effectively to deliver this solution."

Pricing and Availability
The Ethernet Aggregation Reference Design is free and fully documented. Xilinx LogiCore IP must be licensed separately. All documentation and design files are available free of charge and can be easily accessed after registering at the Xilinx web site at http://www.xilinx.com/esp/index.htm.

Xilinx Online Resource for Metro Area Networks Design
In addition to providing high performance silicon, software, and IP, the Xilinx eSP web portal (www.xilinx.com/esp) is a proven resource for engineers, with over seven million visits since its introduction. The latest segment on the eSP web portal is dedicated to accelerating the development of MAN and optical networking products.

About AMIRIX
Founded in 1981, AMIRIX provides custom embedded systems design services for electronic product realization. Core capabilities include high performance board design and integration, programmable logic design, and embedded software design. AMIRIX solutions are flexible, time-to-market efficient, cost effective, and are found in defense, aerospace, medical applications and communications platforms. AMIRIX is also a Xilinx XPERTS Certified Diamond third party design partner. For more information, visit http://www.amirix.com/.

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