FOR IMMEDIATE RELEASE

XILINX RAPIDIO SOLUTION SUCCESSFULLY INTEROPERATES WITH FREESCALE PowerQUICC III PROCESSOR & TUNDRA RAPIDIO SWITCH

Companies Working Together To Enable Real World Deployment of
RapidIO Based Systems

FRANKFURT, Germany, September 28, 2004 - At Euro Smart Network Developer Forum today, Xilinx, Inc. (NASDAQ: XLNX) successfully demonstrated interoperability between its Virtex RapidIO solution, Freescale Semiconductor's PowerQUICC III processor and the Tundra Semiconductor Tsi500 RapidIO switch. The assured interworking between the industry's most widely used embedded processor, the leading RapidIO based switch and the industry's most popular FPGA now allows customers to quickly build their real world communications and processing systems while significantly reducing hardware testing requirements.

The interoperability between the three silicon devices was demonstrated using an industry standard RapidIO Hardware Interoperability Platform (HIP) and GP3 linecard from Silicon Turnkey Express (STx) and a HIP adaptor card from NuHorizons Electronics connected to the Xilinx Virtex-II XLVDS board.

"The GP3 card from STx comprises an ideal, hassle-free development platform for customers who wish to use POWERQUICC III communications processors shipping today with a RapidIO interface," said Lakshmi Mandyam, PowerQUICC III product marketing manager at Freescale Semiconductor. "The GP3 companion card brings the versatile Xilinx Virtex-II into the equation. By combining the PowerQUICC and Virtex-II, system developers can create high-function subsystems for multi-service platforms, access control security systems, load balancing switches and all manner of access/edge networking equipment."

According to Robert Applebaum, president, STx, "For those customers who want the future-proofing capability only possible in a Spartan or Virtex device, as well as leading-edge technology such as RapidIO, Xilinx has delivered a uniquely powerful solution that works seamlessly with leading communications processors such as Freescale's PowerQUICC III products."

"Interoperability between the Tundra RapidIO silicon and Xilinx FPGAs is a significant step forward in bringing RapidIO to our customers as a low risk solution for next-generation system interconnect," said Rick O'Connor, chief technology officer at Tundra. "HIP is designed to facilitate interoperability testing and make it easier for systems designers to validate interoperability and to verify RapidIO system performance."

"Xilinx is committed to delivering the best possible RapidIO solutions to our customers with Virtex-II series FPGAs today and with Virtex-4 in the near future," said Mark Aaldering, vice president of the IP Solutions and Embedded Processing Divisions at Xilinx. "Interoperability testing with other leading solutions is a big portion of that commitment and goes a long way in assuring customers their designs will work right the first time."

About the Demonstration
The demonstration showcases a Freescale MPC8560 PowerQUICC III processor communicating via a simple memory mapped interface and doorbell support to an 8-bit RapidIO endpoint implemented using a Xilinx Virtex-II FPGA through a Tundra TSI500 RapidIO switch. The demonstration uses an off the shelf commercially available HIPPS system from STx and allows immediate access to the Rapid IO features with minimal software.

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