FOR IMMEDIATE RELEASE

XILINX EXTENDS AURORA SERIAL CONNECTIVITY PROTOCOL FOR
10 GIGABITS PER SECOND LINKS & BEYOND

Virtex-II Pro X FPGAs showcase multiple enhancements to the industry's most popular,
open point-to-point serial communications protocol

SUPERCOMM, Chicago, Illinois, June 22, 2004 - Xilinx, Inc. (NASDAQ: XLNX) today announced the extension of its Aurora high-speed serial I/O protocol to enable a wide range of chip-to-chip, backplane, box-to-box and board-to-board connectivity applications to communicate from 600Mbps to 10Gbps per lane. Customer-ready reference designs that showcase the new features on the Xilinx Virtex-II Pro X devices, the industry's first and only FPGA with serial links of up to 10Gbps, are also released today. Aurora has already generated significant momentum in the market with over 3,400 licenses to date and has been used by designers for a diverse range of applications, including medical imaging equipment, wired and wireless infrastructure, broadcast communications systems, video servers, industrial controllers, aerospace and defense applications.

By further scaling the capabilities of this popular high-speed I/O, the FPGA leader underscores its commitment to providing tools and solutions that simplify serial design. Today's announcement also coincides with Xilinx's demonstration of the world's first 10Gbps ATCA backplane at SUPERCOMM 2004 from June 22nd through June 24th (see separate press release).

Scalable, High-Speed Serial I/O Protocol
The Aurora protocol is a scalable, lightweight, link-layer protocol that can be used to transmit data across point-to-point serial lanes while eliminating the resource inefficiencies of other serial protocols. Aurora is an open protocol, licensed at no cost, which can be implemented in any silicon device/technology including FPGAs, ASICs and ASSPs. The new extensions to the Aurora protocol include:

• 64B66B encoding for reduced coding overhead in 10Gbps serial links allowing designers to easily perform trade-offs between error rate and protocol efficiency.
  
  
• Simplex operation for one-way communication link.
  

New, fully parameterized reference designs, delivered through Xilinx's CORE Generator tool, provide 8B10B encoding over multi-lane channels of up to 10Gbps for a Xilinx Virtex-II Pro X device. A single-lane reference design implements 64B66B encoding for the Virtex-II Pro X device family. The new Aurora Bus Functional Model (BFM) includes push-button conformance testing for integration of the protocol into ASIC/ASSP designs as a standard scalable FPGA interface.

"These enhancements to the popular Aurora protocol will make it an even more effective way to future-proof serial backplane designs. For example, systems architects can develop custom switching solutions for a competitive advantage with increased efficiency and reduced latency built into their designs," said Andy DeBaets, senior director of Systems and Application Engineering at Xilinx. "Its use within ATCA-compliant architectures, combined with programmability of the Virtex-II Pro X solution, will reduce cost and risk for developers, and give them even more flexibility in differentiating their products."

Deliverables & Availability
All Aurora deliverables are available free of charge from the Xilinx website at http://www.xilinx.com/aurora upon acceptance of a license agreement. These include the Aurora Protocol Specification, Xilinx LocalLink Interface Specification, Aurora reference designs, and supporting demonstration designs for standard Xilinx development boards. The Aurora bus functional model is also available free of charge.

Xilinx's High-speed Serial Solutions
The Xilinx Serial Tsunami initiative accelerates the industry shift from parallel to serial I/O signaling technologies with next-generation connectivity solutions that support line rates from 622Mbps to 10Gbps and beyond. Xilinx's high performance Virtex-II Pro series of FPGAs deliver advanced features, including IBM PowerPC™ processors immersed into the industry's leading FPGA fabric, multi-gigabit RocketIO™ serial transceivers, and cutting-edge embedded design tools, combined with a suite of IP cores. This comprehensive solution addresses the broad range of connectivity requirements across the entire line to the backplane.