FOR IMMEDIATE RELEASE

XILINX ACQUIRES HIER DESIGN, BRINGS INDUSTRY'S FASTEST, MOST ROBUST DESIGN FLOW TO FPGA DESIGNERS
Hierarchical floorplanner supports Virtex-4 high density / high performance FPGAs

DAC Booth #4343

SAN DIEGO, Calif., June 7, 2004 - Xilinx, Inc. (NASDAQ: XLNX) today announced the acquisition of privately-held Hier Design, a pioneer in hierarchical floorplanning and analysis software for high-performance field programmable gate array (FPGA) design.

Today's news underscores Xilinx's commitment to providing customers with the industry's most comprehensive methodology and tools for platform FPGA-based design through a combination of Xilinx and electronic design automation (EDA) partner solutions. Hier Design's EDA tools exclusively support Xilinx FPGAs, enabling a faster and less iterative path from logic synthesis through physical design by allowing designers to easily comprehend, modify, analyze and implement their FPGAs. Together, Hier's PlanAhead system and Xilinx's ISE design tool suite deliver the fastest, most complete family of integrated FPGA design tools on the market today.

Financial terms of the acquisition were not disclosed, however the acquisition represents less than one percent of the total assets of Xilinx as of the end of its fourth quarter ended April 3, 2004. The company anticipates booking the acquisition in the June 2004 ending quarter. The majority of Hier Design employees, currently located at the company's headquarters in Santa Clara, Calif., will become Xilinx employees within the design software division.

"Xilinx and Hier Design share a unified vision for the critical importance of high-level design and analysis within an FPGA design methodology. Today's merger news represents the next natural progression in a partnership spanning the past three years," said Xilinx Executive Vice President Rich Sevcik. "As an early stage investor in the company, we've had the pleasure of working with Hier Design's stellar R&D team to deliver FPGA solutions to our mutual customers. The company's current customer base is a 100 percent overlap with ours, so our customers will continue to receive the same level of support from Xilinx, complemented by specialized support from the Hier team."

"We've enjoyed a strong relationship with Xilinx and its customer base since our founding and this will only serve to strengthen the capabilities the PlanAhead floorplanner can offer to a wider spectrum of FPGA designers," said Hier Design Co-founder Jackson Kreiter. "I'm confident our employees who are transitioning over to Xilinx, all of whom have made significant contributions to get Hier Design to the stage that we are today, will be valuable contributors to the overall Xilinx design tool and methodology strategy."

"We're delighted to become part of Xilinx and look forward to paving a path toward even more robust solutions for FPGA design," added Hier Design Co-founder and Chief Technology Officer Salil Raje. "With the advent of 90nm FPGAs with up to 200,000 logic cells and up to 500 MHz performance, there's no doubt that floorplanning is as essential to the FPGA flow as it is for state-of-the-art ASIC design."

The acquisition of Hier Design is aptly timed with the debut of an entirely new class of domain-optimized platform FPGAs from Xilinx. The Virtex -4 family FPGA architecture will deliver twice the density and up to twice the performance of any FPGA in the industry currently in production (see separate release XILINX UNVEILS VIRTEX-4 FAMILY -INDUSTRY'S FIRST MULTI-PLATFORM FPGA). Enabled by the revolutionary Advanced Silicon Modular Block (ASMBL™) architecture, the Virtex-4 product line will be the world's first FPGA family with multiple domain-optimized platforms, offering breakthrough FPGA capability at every price point. The complexity and integration capabilities of such devices require new and innovative design strategies.

Hier has been a member of Xilinx's Alliance EDA program since its founding in 2001, when Xilinx became an initial investor in the company. Already, the PlanAhead software offers seamless integration with the Xilinx design flow by encapsulating place-and-route commands directly in the GUI, and utilizes synthesized results from other Xilinx design partners. Hier Design's technology, which was recently enhanced with timing analysis capabilities, will be integrated with Xilinx's ISE design environment to enable the highest quality of design results with the least time and effort. The PlanAhead floorplanner is currently being used extensively by customers in support of the latest Xilinx Virtex-II , Virtex-II Pro , and Spartan-3 device families, and it will support the new Virtex-4 family.

Further Penetration into ASIC segment
The introduction of highly complex devices such as Virtex-4 family, and advanced design methodologies such as those supported by Hier's tools, further bolster Xilinx's strategy to move beyond the $5.1B programmable logic segment and capture additional share in the $36B ASIC and ASSP segments*. System designers within high-growth technology segments such as wired and wireless communications, storage and multimedia will now be able to use cost-effective FPGAs for applications previously served only by ASICs and ASSPs.

New FPGA design challenges require new approaches
With up to 200,000 logic cells on a 90nm process operating at up to 500 MHz performance, devices such as Xilinx's new Virtex-4 family introduce new design challenges, including: slow or unpredictable routing results, routing congestion, tightly packed designs, heavily-constrained interconnect, clock complexity, critical paths spanning hierarchy, and the inability to maintain design performance.

The PlanAhead floorplanner reduces the length and number of design iterations by giving designers advanced insight into the place and route process. Designers can quickly examine multiple "what if" scenarios about physical design, enabling them to identify and fix potential problems beforehand. They can also group critical paths and modules to increase routability through connectivity analysis and utilization control.

The PlanAhead software provides a hierarchical, block-based and incremental design methodology, enabling designers to change only one part of the design and leave the rest intact, shortening design iterations.

About ISE
The ISE design environment provides the fastest, most complete, integrated family of design tools available anywhere. It lets you take advantage of leading Xilinx solutions such as the Spartan-3 FPGA device family-offering the lowest cost per gate and per I/O - and the Virtex II Pro family, which offers the lowest system cost in an FPGA. Plus, the ISE 6 solution provides the fastest performance in the market today. With the ISE 6 software and Virtex-II Pro Platform FPGAs, you can realize design performance of over 400 MHz and up to 10 Gbs serial I/O, the lowest system cost with the highest performance.

About Hier Design
Founded in 2001, Hier Design Inc. is an electronic design automation (EDA) industry newcomer creating the next EDA beachhead by helping fuel the movement from application specific integrated circuits (ASICs) to high-speed, highly complex field programmable gate arrays (FPGAs). Corporate headquarters is located at: 2350 Mission College Boulevard, Suite 850, Santa Clara, Calif. 95054. Telephone: (408) 982-8240. Facsimile: (408) 982-3838. Email: info@hierdesign.com. More details can be found at the Hier Design website located at: http://www.hierdesign.com.

# 0468
*Market Data Source: Gartner Dataquest 2007 Projection