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Richard Griffin Designing a Custom Processor Peripheral Using Xilinx EDK Part 2
This TechXclusive describes how to design a custom peripheral for use in an embedded processor system, then looks at some more advanced topics, including using the template generated by the Embedded Development Kit tools, writing software drivers for the created peripheral, and enabling the Embedded Development Kit tools to add the peripheral to its library of IP. Part 2 focuses on LCD user registers.
Author: Richard Griffin Part 1 Part 2
Austin Lesea and Peter Alfke Rosetta: Soft-Error Test Update
In 2002, Xilinx embarked on a large-scale project to test the integrity of FPGA configuration data when exposed to cosmic and solar radiation. Experiments in high-energy test chambers have demonstrated Single Event Upsets (SEUs) or soft errors, so the Xilinx project's objective is to test FPGAs using Virtex-IIâ„¢ and Virtex-II Proâ„¢ devices in real-life conditions. This article discusses the results to date.
Author: Austin Lesea and Peter Alfke
Saar Drimer Theoretical Cryptography from an FPGA Perspective
Academia is constantly evaluating theoretical attacks against cryptographic methods and algorithms. However, theoretical attacks are just that – theoretical, and they must be put into perspective by applying a measure of real-world practicality. "Practicality" means the further analysis of two major factors: the value of the data protected, and for how long the data must to be protected.
Author: Saar Drimer
 
     
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Previous Articles
TITLE
Designing a Custom Processor Peripheral Using Xilinx EDK
10/18/2004
Rosetta: Soft-Error Test Update
08/16/2004
Theoretical Cryptography from an FPGA Perspective
08/02/2004
Get Your Priorities Right - Make your design up to 50% smaller
07/08/2004
That is So Random!
06/11/2004
"The Battery Case"
05/17/2004
Timing Closure - 6.1i
04/07/04
The Eyes Have It!
03/18/2004
Bit Error Rate: What is it? What Does it Mean?
03/03/2004
The Old 35 pF Just Disappeared
01/23/2004
Multiplexer Selection
01/07/2004
Power to the People -- Not to the FPGA!
10/27/2003
Programmable Development and Test
09/12/2003
It's Not Your Father's PCB Anymore...
08/28/2003
Reconfiguring Block RAMs
07/17/2003
Magic Numbers
04/21/2003
Six Easy Pieces (Non-Synchronous Circuit Tricks)
04/02/2003
Printed Circuit Board Modeling Issues
03/19/2003
A Thousand Years Between Single-Event Upset Failures
02/03/2003
Digitally Removing a DC Offset (or "DSP Without Math?")
02/03/2003
What are Virtex and Spartan-II I/O Pins Doing?
01/10/2003
IBIS Model Usage
11/13/2002
Metastability Delay and Mean Time Between Failure in Virtex-II Pro FFs
10/28/2002
Those Tiny Little Vias can Cause Big Ground Bounce Problems
10/11/2002
Relationally Placed Macros
08/30/2002
Creating Embedded Microcontrollers (Programmable State Machines)
07/28/2002
Timing Closure
01/24/2002
Performance + Time = Memory (Cost saving with 3-D design)
01/04/2002
Does Your Design Have Enough Slack?
11/05/2001
Evolution and Revolution: Recent Progress in Field-Programmable Logic
10/19/2001
Get Smart About Reset (Think Local, Not Global)
10/03/2001
Asynchronous FIFO in Virtex-IIâ„¢ FPGAs
08/20/2001
Moving Data Across Asynchronous Clock Boundaries
07/10/2001
Expanding Virtex-IIâ„¢
06/30/2001
FPGAs Driving Voice-Data Convergence
06/04/2001
Jitter - Variations in the significant instants of a clock or data signal
04/23/2001
Using Leftover Multipliers and Block RAM in Your Design
04/23/2001
Colour Space Conversion
03/26/2001
"8x12 Does NOT Equal 12x8"
02/12/2001
Printed Circuit Board Considerations
01/15/2001
Signal Integrity Tips and Tricks
12/28/2000
Saving Costs with the SRL16E
12/27/2000
Choices, Choices and Opinions
10/30/2000


 
       
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